|
|
 |
|
Backside
Via-Hole Process
Backside
Capacity Plan
| PHASE
I |
300
Wafers per Week
|
| PHASE
II |
800
Wafers per Week
Q4,2000
|
| PHASE
III |
1500
Wafers per Week
Q2,2001
|
-
|
|
[
Home
] [
About AWSC
] [
Technology Information
] [
Quality Assurance
] [
Foundry Service
] [
Human Resource
] [
News
]
Sed mail to webmaster@awsc.com.tw with
question or comments about this web site.
Copyright 1999 Advanced Wireless Semiconductor Commpany
Last modifired: 2005/03/11
|
